The invention mainly relates to complementary metal oxide semiconductor (CMOS) amplifiers and, in particular, is useful in bipolar CMOS (BiCMOS) forms of integrated circuit (IC) construction. In this latter circuit form a CMOS wafer is designed to include bipolar transistors along with insulated gate monopolar transistors so that the integrated circuits can have the advantages of both of the basic configurations.
Typically, operational amplifiers (op-amps) have taken the form shown in FIG. 1. A differential input stage 10 is followed by a gain stage 11 which drives a unity-gain output stage 12 that is capable of supplying a suitable power output at terminal 16 to load 13. Terminals 14 and 15 respectively comprise the inverting - and noninverting + differential inputs. The op-amp is operated from a power supply connected via supply lines 8 for + V.sub.CC and 9 for -V.sub.SS. FIG. 2A is a block diagram wherein the op-amp is connected as a unity gain inverter which functions as a voltage follower. For the connections shown, where the output 16 is connected directly to the inverting input, the output voltage at terminal 16 will closely follow the voltage at terminal 15. By way of example, using a 13.5 k ohm resistor as load element 13, the op-amp will supply a +3.1 volt output capability when using +5 volt supplies. A ground reference exists midway between +V.sub.CC and -V.sub.SS.
FIG. 2B shows the op-amp connected as an inverting amplifier. Here a pair of resistors, 17 and 18, couple output terminal 16 to input terminal 14'. The resistor juncture is connected to the inverting input 14 of the op-amp and the non-inverting input 15 is grounded. The gain of the inverter is determined by the relative values of resistors 17 and 18. When they are equal the gain is unity.
FIG. 2c shows a charge inverter version of an op-amp. Capacitors 17' and 18' couple output terminal 16" to input terminal 14". The capacitor juncture is connected to the inverting input of the op-amp and the noninverting input is grounded. The gain of the inverter is determined by the relative values of capacitors 17' and 18'. When they are equal the gain is unity.
It is common practice to employ cascoded input and gain stages in the op-amp to provide good power supply rejection ratios along with high signal gain and low noise performance. As is typical in op-amp design, capacitive feedback is employed for frequency compensation. U.S. Pat. No. 4,484,148, which is assigned to the assignee of the present invention, shows such compensation. The teaching in this patent is incorporated herein by reference.
FIG. 3 is a schematic diagram showing a typical CMOS version of stages 10 and 11 of FIG. 1A. Unity gain output stage 12 is conventional and will not be further described herein. The input stage 10 includes P channel transistors 20 and 21, the gates of which are driven from the inverting and noninverting inputs 14 and 15 respectively. N channel transistors 22 and 23 form a conventional current mirror load which provides the differential to single ended output conversion and acts to drive the gate of N channel gain transistor 24.
P channel transistor 25, which is biased into conduction by the potential at terminal 26, is connected to the common sources of transistors 20 and 21 thereby to operate them differentially. Thus, transistor 25 is the tail current source for the differential input stage 10.
P channel transistor 27 has its gate biased in parallel with that of transistor 25 so that it too acts as a current source for gain stage 11. Thus, transistor 27 is the load element for transistor 24 and the stage output 19 is taken from the drain of transistor 27. Transistor 28 is cascode connected to transistor 24 and its gate is referenced at ground. Thus, gain stage 11 is cascoded thereby deriving the benefits of cascode operation.
P channel transistors 29 and 30 are respectively cascode connected between the drains of transistors 20 and 21 and load transistors 22 and 23 to provide a cascode connected input stage 10. The gates of transistors 29 and 30 are biased by the potential at terminal 31 to ensure that they remain saturated throughout the normal operating range of the input stage.
Capacitor 32 is the op-amp frequency compensation element. It will be noted that transistor 30 acts as a common gate amplifier to couple the left hand terminal of capacitor 32 to the gate of transistor 24. Thus, the cascode transistor 30 serves the dual function which additionally isolates the compensation capacitor from the output of input stage 10 and cascode couples transistor 21 to load transistor 23. Thus, capacitor 32 does not present significant capacitive loading to input stage 10. This action is detailed in above-mentioned U.S. Pat. No. 4,484,148.
The circuit of FIG. 3 functions well as an op-amp and has proven useful as a circuit in its own right. However, when connected as shown in FIG. 2A, as a unity-gain amplifier device, it suffers from some drawbacks in terms of transient response performance. For large transients the circuit of FIG. 2B suffers similar drawbacks, but to a lesser degree.
FIG. 4 is a graph showing the output of the FIG. 1 circuit when subjected to relatively large input steps. The steps start at zero and include a +2-volt step at T1, a 1.1-volt step at T2, a -0.9-volt step at T3, a -2-volt step at T4 and, finally, a -2-volt step at T5. Thus, the range of 0 to 3.1 volts to -3.1 volts is covered. The time intervals shown involve 4 .mu.s increments. The circuit slew rate is typically about 3 volts per microsecond. As shown in FIG. 4, the positive steps are followed fairly well with only small transient overshoots appearing at the output. However, the negative steps show a different matter. The -0.9-volt step at T3 shows ringing following the transient. The negative 2-volt step at T4 is followed by substantial ringing and the subsequent negative three volt step at T5 is followed by transient ringing. It was concluded that when a positive step is applied to the gate of transistor 21, the tail current from transistor 25 will flow into load transistor 22. This current is mirrored by transisistor 23 which will pull the gate of transistor 24 low towards cutoff. This allows transistor 27 to pull the right hand end of capacitor 32 high. Capacitor 32 will couple this rise to the source of transistor 30 thereby turning it on and it will pass a current which will charge the capacitor. Since capacitor 32 is fully operative in this set of conditions the frequency compensation will function and the circuit will be stabilized.
However, for a negative input transition to the gate of transistor 21, the tail current from transistor 25 will be diverted away from transistor 20 and, therefore, the current in transistor 22 will cease. So, too, will the current in transistor 23. As a result, transistor 30 will be cut off and the negative feedback loop around the drain to gate circuit of transistor 24 will be opened and transistor 24 will tend to oscillate. This shows up as ringing that follows the negative transient input.